1. Field of the Invention
The present invention relates to a pull-up circuit which raises the potential of a given node in a circuit to a given level and a semiconductor device having such a pull-up circuit.
Semiconductor devices can operate with a reduced power supply voltage in advance of the production process thereof. Under the above situation, there is a case where a system is configured by using semiconductor devices that operate with different power supply voltages.
2. Description of the Related Art
FIG. 1 is a block diagram of a system in which semiconductor devices operating with different power supply voltages are connected together through a bus. The system shown in FIG. 1 is formed on a circuit board. Semiconductor devices A and B are connected together through a bus 10, via which data is transferred therebetween. The semiconductor devices A and B operate with different power supply voltages. For example, the semiconductor device B operates with a power supply voltage of 5 V, and the semiconductor device A operates with a power supply voltage of 3.3 V. When the semiconductor device B outputs data to the bus 10, it drives the potential of the bus 10 to 0 V or 5 V in accordance with the data to be output. When the high potential and low potential of the bus 10 are respectively denoted as Vh and Vl, the semiconductor device B drives the bus 10 so that Vh=5 V and Vl=0 V. Similarly, when the semiconductor device A outputs data to the bus 10, the semiconductor device A drives the bus 10 so that Vh=3.3 V and Vl=0 V.
Generally, the semiconductor devices A and B are equipped with pull-up circuits located in interface parts thereof. In FIG. 1, the internal structure of the semiconductor device A is illustrated for the sake of simplicity. The semiconductor device A has a connection terminal 16 to which the bus 10 is connected. An internal circuit of the semiconductor device A is electrically connected to the bus 10 via the terminal 16. The semiconductor device A has a buffer 12 and a pull-up circuit 14, which are connected to the terminal 16 and form an interface with the bus 10. The buffer 12 is, for example, an input buffer or an output buffer and may be an input/output (bidirectional) buffer. Data on the bus 10 is latched in the buffer 12 via the terminal 16, and is supplied to an internal circuit (not shown) of the semiconductor device A.
The pull-up circuit 14 functions to pull up the potential of the terminal 16 to the power supply voltage of the semiconductor device A. In the case where the semiconductor device A operates with a power supply voltage of 3.3 V, the pull-up circuit 14 pulls up the potential of the terminal 16 to 3.3 V (=Vdd). Hence, it is possible to prevent the potential of the terminal 16 from being at an intermediate level between 0 V and 3.3 V due to a certain factor. If the potential of the terminal 16 becomes such an intermediate level, the buffer 12 and/or the internal circuit may malfunction or wasteful power may be consumed therein.
As shown in FIG. 1, the pull-up circuit 14 is formed of a P-channel MOS transistor (hereinafter, simply referred to as PMOS transistor) or an N-channel MOS transistor (NMOS transistor). When the pull-up circuit 14 is formed of the PMOS transistor, the source thereof is supplied with the power supply voltage Vdd (=3.3 V in the above example), and the gate thereof is fixed at a potential Vss (equal to, for example, 0 V). The drain of the PMOS transistor is connected to the terminal 16. Hence, the PMOS transistor is ON, and pulls up the potential of the terminal 16 to the power supply voltage Vdd. When the NMOS transistor is used, the gate thereof is fixed to the power supply voltage Vdd so that it is ON.
However, the conventional pull-up circuit 14 has the following disadvantages.
As has been described previously, the potential of the bus 10 can be set to 5 V. For example, the semiconductor device B drives the bus 10 to its power supply voltage equal to 5 V. At that time, the potential of the terminal 16 becomes equal to 5 V. If the pull-up circuit 14 is formed of the PMOS transistor, the drain thereof is supplied with a voltage of 5 V. Generally, the back gate voltage of the PMOS transistor is fixed to the power supply voltage, which is equal to 3.3 V in the present example. That is, the drain of the PMOS transistor of the pull-up circuit 14 is at 5 V, while the back gate thereof is at 3.3 V. Hence, a current path directed to the back gate (an N-type well) from the drain is formed. In other words, a diode is connected between the drain and back gate of the PMOS transistor in the forward direction. A current flows in the above current path from the bus 10 to the power supply Vdd. Such a current degrades the reliability of the PMOS transistor and decreases the potential of the bus 10.
There is also a case where another current flows from the drain of the PMOS transistor to the power supply Vdd via the source thereof. When the drain of the PMOS transistor is at 5 V and the source thereof is at 3.3 V (=Vdd), a current path from the drain to the source. When such a current is also considered, the thickness of an oxide film of the PMOS transistor may be increased, or a specific pull-up circuit may be provided to pull up the potential of the bus 10 to 5 V. However, these means may be not practical in terms of the production cost and are not capable of preventing the occurrence of the current itself.
When the pull-up circuit 14 is formed of the NMOS transistor, the source potential thereof is higher than the drain potential thereof, and thus the occurrence of the above currents flowing from the bus 10 can be prevented. However, the NMOS transistor has only a capability of pulling up the bus 10 to a voltage defined by subtracting the threshold voltage of the NMOS transistor from the gate potential (set equal to the power supply voltage Vdd) thereof. Hence, the pull-up circuit 14 formed of the NMOS transistor cannot sufficiently perform the pull-up operation. For example, if the power supply voltage Vdd which is normally equal to 3.3 V is temporarily decreased to 3.0 V, the NMOS transistor can pull up the bus 10 to only 2.5 V with the threshold voltage thereof equal to 0.5 V. Such an intermediate potential functions as an indefinite potential with respect to an internal circuit connected to the buffer 12, and the internal circuit may malfunction.